[dv] Add testing and coverage for direct mode mtvec from #2044
Open
Nobody has claimed this yet.
Component:DV
Type:Task
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
The PR https://github.com/lowRISC/ibex/pull/2044 adds support for direct mode mtvec where all interrupts go to the same handler address.
This features needs to be stimulated in DV and coverage added before we can merge the PR.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading PR #2044 to understand the direct-mode mtvec support and its existing verification context. Add DV stimulation for the feature and coverage demonstrating that direct mode routes interrupts to the same handler address; the coverage results should show the feature is exercised before the PR can merge.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100