Hamming distance between (critical) instructions
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- SystemVerilog
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Description
IIUC opcode encodings for various branch instructions are
| instruction | `opcode` | `funct3` |
|-|-|-|
|`beq`|`1100011`|`000`|
|`bne`|`1100011`|`001`|
|`bge`|`1100011`|`101`|
Obviously other instructions can also be _critical_ depending on the context but the table above shows that the HDs of instructions that are used most often for hardening in SW are 1 or 2 bits.
In contexts where active physical attacks such as fault injection are within the scope of the threat model, a larger hamming distance between opcodes is highly desirable. Such a change, however, is far from trivial and would obviously impact the toolchain and RISC-V ISA compatibility among other things. I'm creating this issue to explore this idea and understand if this is something we would like to pursue.
cc @moidx @cfrantz @arunthomas
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue names no files, tests, or entry points. Compare the listed branch opcode/funct3 encodings, then assess whether greater Hamming distance is compatible with the toolchain and RISC-V ISA; done means a decision on whether to pursue the idea.
Written by the indexing model from the issue text.
Assessment
- Domain
- compilers, security
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100