[dv] Verify data_rvalid_i hardening
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Component:DV
Priority:P3
Type:Task
- Dominant language
- SystemVerilog
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- Avg merge
- 5d 23h
- Merged PRs (30d)
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Description
This PR: https://github.com/lowRISC/ibex/pull/1968 altered the handling of data_rvalid_i so that it will only cause a register write if a load is expected. Add a test that glitches data_rvalid_i when a load isn't in progress to verify this hardening.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading PR 1968 and the surrounding verification work for data_rvalid_i. Add a regression test that glitches data_rvalid_i while no load is in progress, then verify that no register write occurs; the test should pass with the hardening in place.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100