Support for riscv-formal
Open
Nobody has claimed this yet.
Component:DV
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
Is it possible to support the [RISC-V Formal Verification Framework](https://github.com/cliffordwolf/riscv-formal)? If yes, are there plans to do this?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing Ibex's existing verification setup and the linked RISC-V Formal Verification Framework. Determine whether support is technically feasible, what integration scope would be required, and which verification outcomes would define completion; the issue does not name files, tests, or an implementation entry point.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 10/100