[rtl] Check and fix IRQ entry latency for 2-stage config
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Component:RTL
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
In #1304 , we discussed that there might be an additional cycle of latency added when entering and interrupt handler in the 2-stage configuration. See https://github.com/lowRISC/ibex/pull/1304#discussion_r594375140 for more details.
We should check if this can be fixed easily.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with issue #1304 and the linked discussion about IRQ entry latency, then inspect the RTL for interrupt entry in the 2-stage configuration. Measure whether an additional cycle occurs and compare it with the expected behavior. Done means the latency is either corrected or the reason it cannot be fixed easily is documented.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100