[syn] Add more robust error detection/reporting to synthesis flow
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- Dominant language
- SystemVerilog
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Description
The synthesis flow uses a variety of python, shell and TCL scripts that expect certain things to be correct. When it breaks the errors it produces don't obviously point to the problem (as illustrated by https://github.com/lowRISC/ibex/issues/1193)
More thought should be put into detecting issues at the point they occur in the flow so sensible error reporting can occur.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the Python, shell, and TCL scripts that make up the synthesis flow, using issue #1193 as the failure example. Identify where the current flow detects failures and define what clearer reporting should look like at those points. Done means the relevant failures are detected close to their cause and produce sensible, actionable errors.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- python, shell
- Domain
- build-system, tooling
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100