[docs] Clean up line breaks
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- SystemVerilog
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Description
The source files for the documentation have a mix of styles for when lines should be broken, the verification page is a notable example: https://raw.githubusercontent.com/lowRISC/ibex/master/doc/03_reference/verification.rst which contains wrapping lines at different lengths as well as the one line for one sentence style.
Line breaking style should be checked and made consistent across all documentation files (ensuring all files comply with one line for one sentence).
We could consider a CI check to ensure documentation files are correctly formatted.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the linked doc/03_reference/verification.rst file, then inspect the other documentation source files for their line-breaking styles. Make documentation consistent with one line per sentence across all files; the optional CI check is a separate consideration.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100