riscv_mmu_stress_test test fail
Open
Nobody has claimed this yet.
Component:DV
Type:Bug
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
Hi ,
when IBEX_CONFIG=small, SEED=27754, ISS=OVPSIM, riscv_mmu_stress_test test failed.
it is failed because there are some mismatches between rtl sim csv log and ovpsim csv log, could you please help double check if it is a RTL issue or test case issue?
Thanks,
Lihua
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Reproduce riscv_mmu_stress_test with IBEX_CONFIG=small, SEED=27754, and ISS=OVPSIM, then compare the RTL simulation and OVPSIM CSV logs. Trace each mismatch to determine whether the RTL or test case is responsible; done means the failure is explained and the appropriate issue is identified.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100