Illegal Instruction Retires
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Since Oct 14, 2020.
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Description
#### RISC-V Specification
> 3.1.11: "The minstret CSR counts the number of instructions the hart has retired. The mcycle and minstret registers
have 64-bit precision on all RV32 and RV64 systems.
> The counter registers have an arbitrary value after system reset, and can be written with a given value. Any CSR write takes effect after the writing instruction has otherwise completed."
> The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register.
> When the CY, IR, or HPMn bit in the mcountinhibit register is clear, the cycle, instret, or hpmcountern register increments as usual. When the CY, IR, or HPMn bit is set, the corresponding counter does not increment.
#### Issue Description
An illegal instruction increments the minstret counter as if it was a legal one.
#### Steps to Reproduce
As shown below, the minstret counter is incremented for the illegal instruction csrrw x8, 0x010, x3, knowing that IR bit of mcountinhibit is set to '0 and thus allowing for the minstret to be incremented.
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Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2020.2.0
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