Enable a way to configure the Cache characteristics from the Ibex Core Top
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- SystemVerilog
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Description
Simply I noticed this in the Ibex. The cache is fixed always to:
```
module ibex_icache #(
// Cache arrangement parameters
parameter int unsigned BusWidth = 32,
parameter int unsigned CacheSizeBytes = 4*1024,
parameter bit ICacheECC = 1'b0,
parameter int unsigned LineSize = 64,
parameter int unsigned NumWays = 2,
// Always make speculative bus requests in parallel with lookups
parameter bit SpecRequest = 1'b0,
// Only cache branch targets
parameter bit BranchCache = 1'b0
)
```
The cache is only instanced in the following line.
https://github.com/lowRISC/ibex/blob/master/rtl/ibex_if_stage.sv#L185
The parameters are not controlled definitely in any external way possible. It would be neat to control the size of the cache from the parameters. Is this the way intended?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start at rtl/ibex_if_stage.sv around line 185 and inspect how ibex_icache is instantiated. Compare the cache parameters listed in the issue with the parameters exposed by the Ibex Core Top. Done means the cache characteristics can be configured externally rather than remaining fixed at the instantiation defaults.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100