Does NMI need to be precise?

Nobody has claimed this yet.

Currently our NMI is much like other interrupts. In that you will get an architectural state that corresponds to what is was immediately before the instruction `mepc` points to executes. This means you can easily resume execution outside of the interrupt by jumping back to to `mepc` provided you restore the register state to what is was before you did anything in the interrupt handler. This is a precise interrupt (which I don't think is defined in the RISC-V spec but clearly you don't want normal interrupts to be imprecise).

Do we want NMI to be precise? The privileged spec states NMI will 'cause an immediate jump to an implementation-defined NMI vector running in M-mode'. Currently if we have an outstanding memory request we will wait for the response before executing any of the interrupt handler code (simply due to the pipeline structure). In particular if we want precise exceptions on bus errors we'd be waiting to see if there's an error response to handle the bus error exception before taking the NMI.

I think it would be reasonable to make NMI imprecise/unrecoverable, we could also then drop the specialised behaviour we have on NMI where we're in a special NMI mode that restores some CSR state from the mstack registers.

Start by reviewing the current NMI pipeline behavior described in the issue, including outstanding memory requests, precise bus-error handling, the M-mode NMI vector, and mstack CSR restoration. Compare these behaviors with the privileged specification, then document or implement a decided precise-versus-imprecise NMI policy and verify that interrupt recovery semantics are consistent.

Written by the indexing model from the issue text.