lowRISC / lowRISC/fpga-zynq

which version of the fesvr you used in zedboard

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Dominant language
Verilog
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Description

Hello,
I got the LowRISC's RISC-V working on my zedboard, and it was able to run bare-metal or Linux. Thank you.

I am actually debugging the Linux system that has RISC-V chip on our customized FPGA boad, the Spartan 6 is used to place the RISC-V core. Actually, our project is very close to what you guys did on Zedboard. After a bunch of tests, the bare-metal and pk are working fine, but we got stuck in booting the Linux. In order to dig the Linux details, we need to add some printf lines in fesvr's source code to track the HTIF packets between the RISC-V and Host(ARM), and we initially want to focus on that in your LowRISC's RISC-V core run. However, in your manual, the riscv-fesvr is not the correct version, it seems already out-of-date, could you tell me what exactly the version or commit number you used for your zedboard implementation? Thanks in advance.

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Research direction

The issue names the manual, riscv-fesvr, and the Zedboard implementation but no repository file or test. Start by comparing the manual's referenced fesvr version with the Zedboard history or commits; done means identifying the exact version or commit used.

Written by the indexing model from the issue text.

Assessment

Tech stack
linux
Domain
embedded-iot, operating-systems
Issue type
Documentation
Difficulty
1/5
Estimated time
Under an hour
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
20/100

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