[CIR] Implement handling of AArch64 (Arm) SVE intrinsics

### Overview
This is an umbrella issue for implementing ClangIR code-gen for AArch64 [SVE](https://support.arm.com/architectures/scalable-vector-extensions) builtins.

There are enough AArch64 SVE builtins that creating a separate issue for each logical group is not practical. Multiple contributors can work on this in parallel, provided that we coordinate to minimise overlap. To help with this, the table below tracks intrinsics that have already been implemented or are currently being worked on.

If you would like to contribute, please comment indicating which intrinsics(s) you plan to work on.

Before starting work, please check the table below to make sure that no one else is already working on the same intrinsics. If you have any questions, please comment here and tag @banach-space.

### List of intrinsics

| Intrinsic Group | Common prefix | Assignee | PR(s) | Status |
|-------------------------|---------------|----------|-------|--------|
| [svdup](https://developer.arm.com/architectures/instruction-sets/intrinsics#f:@navigationhierarchiessimdisa=[SVE]&q=svdup[) + [svdup_lane](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[SVE]&q=svdup_lane) (exc. SVE2) | `svdup` | @banach-space | #223932 | ✓ (exc. SVE2) |
| [svlen/svcnth](https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svcnth) | `svlen` | @banach-space | | WIP |

https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svcnth

### How to identify intrinsics to implement?

Identifying intrinsics to implement is complicated by the fact that, unlike for Neon, there is no single central list of all possible intrinsic variants (see, for example, this [page](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html) for Neon).

Instead, you will need to cross-check the following resources:

* The [List of Instructions](https://arm-software.github.io/acle/main/acle.html#list-of-instructions) in the ACLE specification.
* The intrinsics specification available at https://developer.arm.com/architectures/instruction-sets/intrinsics.
* The pre-existing [SVE test files](https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/AArch64/sve-intrinsics).

When browsing resources such as https://developer.arm.com/architectures/instruction-sets/intrinsics, please pay attention to the distinction between plain [SVE](https://support.arm.com/architectures/scalable-vector-extensions), [SVE2](https://support.arm.com/documentation/102340/0100/Introducing-SVE2), and [SME](https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-scalable-matrix-extension-introduction). Please always make it clear whether a contribution implements **plain SVE** or one of the later extensions.

### Implementation requirements

1. For each intrinsic listed in the [List of Instructions](https://arm-software.github.io/acle/main/acle.html#mapping-of-sve-instructions-to-intrinsics) in the ACLE specification for SVE, ensure that all variants are supported and tested. The variants are listed at https://developer.arm.com/architectures/instruction-sets/intrinsics; use the links from the [List of Instructions](https://arm-software.github.io/acle/main/acle.html#mapping-of-sve-instructions-to-intrinsics), which include the necessary filters.
2. Reuse the existing AArch64 builtin tests under [clang/test/CodeGen/AArch64](https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/AArch64), in particular those in [clang/test/CodeGen/AArch64/sve-intrinsics/](https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/AArch64/sve-intrinsics). These tests should be moved to the new [SVE subdirectory](https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/AArch64/sve), which enables ClangIR testing. For more context, see https://github.com/llvm/llvm-project/issues/179952.
3. Prefer to preserve the high-level structure of https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp so that switch cases and handling remain visibly consistent with https://github.com/llvm/llvm-project/blob/main/clang/lib/CodeGen/TargetBuiltins/ARM.cpp. Limited refactoring is allowed where it improves maintainability, but it should be explained in the PR description.
4. Format tests using the existing style; see https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/AArch64/sve/dup.c for reference.

### References
* Previous umbrella ticket for Neon: https://github.com/llvm/llvm-project/issues/185382
* SVE documentation: https://support.arm.com/architectures/scalable-vector-extensions
* "The ARM Scalable Vector Extension": https://arxiv.org/pdf/1803.06185 (very good overview of the design principles of SVE).

CC @andykaylor @kiranchandramohan

Choose an unclaimed plain-SVE intrinsic group, then read clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp alongside clang/lib/CodeGen/TargetBuiltins/ARM.cpp. Review the matching files under clang/test/CodeGen/AArch64/sve-intrinsics and the formatting example clang/test/CodeGen/AArch64/sve/dup.c. Done means all variants in the selected group are supported and tested in the new sve test subdirectory.

Written by the indexing model from the issue text.