[hexagon] Assertion `isSimple()` in HexagonTargetLowering::combineConcatVectorsBeforeLegal

This assertion hits when compiling tramp3d w/QFloat - https://github.com/llvm/llvm-test-suite/tree/85dc6675d0577ff391c4e84180ba55f74e70d7ac/MultiSource/Benchmarks/tramp3d-v4

```
./bin/llc -mtriple=hexagon-unknown-linux-musl -mcpu=hexagonv68 -mattr=+memops,+hvxv68,+hvx-length128b,+hvx-qfloat -O3 ../llvm-project/llvm/test/CodeGen/Hexagon/hvx-concat-nonsimple-type.ll -o /dev/null
[4/4] Linking CXX executable bin/llc
llc: /local/mnt/workspace/upstream/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:340: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0. Program arguments: ./bin/llc -mtriple=hexagon-unknown-linux-musl -mcpu=hexagonv68 -mattr=+memops,+hvxv68,+hvx-length128b,+hvx-qfloat -O3 ../llvm-project/llvm/test/CodeGen/Hexagon/hvx-concat-nonsimple-type.ll -o /dev/null
1. Running pass 'Function Pass Manager' on module '../llvm-project/llvm/test/CodeGen/Hexagon/hvx-concat-nonsimple-type.ll'.
2. Running pass 'Hexagon DAG->DAG Pattern Instruction Selection' on function '@f'
#0 0x000056400d320898 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (./bin/llc+0x2990898)
#1 0x000056400d31d609 llvm::sys::RunSignalHandlers() (./bin/llc+0x298d609)
#2 0x000056400d3212ab SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
#3 0x00007f43457b9520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
#4 0x00007f434580d9fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
#5 0x00007f434580d9fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10
#6 0x00007f434580d9fc pthread_kill ./nptl/pthread_kill.c:89:10
#7 0x00007f43457b9476 gsignal ./signal/../sysdeps/posix/raise.c:27:6
#8 0x00007f434579f7f3 abort ./stdlib/abort.c:81:7
#9 0x00007f434579f71b _nl_load_domain ./intl/loadmsgcat.c:1177:9
#10 0x00007f43457b0e96 (/lib/x86_64-linux-gnu/libc.so.6+0x39e96)
#11 0x000056400ea24577 llvm::HexagonTargetLowering::combineConcatVectorsBeforeLegal(llvm::SDValue, llvm::TargetLowering::DAGCombinerInfo&) const HexagonISelLoweringHVX.cpp:0:0
#12 0x000056400ea25c1d llvm::HexagonTargetLowering::PerformHvxDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const HexagonISelLoweringHVX.cpp:0:0
#13 0x000056400e9dfdfa llvm::HexagonTargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const HexagonISelLowering.cpp:0:0
#14 0x000056400e469a25 (anonymous namespace)::DAGCombiner::combine(llvm::SDNode*) DAGCombiner.cpp:0:0
#15 0x000056400e466690 llvm::SelectionDAG::Combine(llvm::CombineLevel, llvm::BatchAAResults*, llvm::CodeGenOptLevel) (./bin/llc+0x3ad6690)
#16 0x000056400e56bca9 llvm::SelectionDAGISel::CodeGenAndEmitDAG() (./bin/llc+0x3bdbca9)
#17 0x000056400e56adb5 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (./bin/llc+0x3bdadb5)
#18 0x000056400e5680d1 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (./bin/llc+0x3bd80d1)
#19 0x000056400eb22624 llvm::HexagonDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) HexagonISelDAGToDAG.cpp:0:0
#20 0x000056400e56595c llvm::SelectionDAGISelLegacy::runOnMachineFunction(llvm::MachineFunction&) (./bin/llc+0x3bd595c)
#21 0x000056400d998836 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (./bin/llc+0x3008836)
#22 0x000056400d634146 llvm::FPPassManager::runOnFunction(llvm::Function&) (./bin/llc+0x2ca4146)
#23 0x000056400d63c3c2 llvm::FPPassManager::runOnModule(llvm::Module&) (./bin/llc+0x2cac3c2)
#24 0x000056400d634d91 llvm::legacy::PassManagerImpl::run(llvm::Module&) (./bin/llc+0x2ca4d91)
#25 0x000056400d327a31 llcMain (./bin/llc+0x2997a31)
#26 0x000056400d268e2f main (./bin/llc+0x28d8e2f)
#27 0x00007f43457a0d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
#28 0x00007f43457a0e40 call_init ./csu/../csu/libc-start.c:128:20
#29 0x00007f43457a0e40 __libc_start_main ./csu/../csu/libc-start.c:379:5
#30 0x000056400d268d25 _start (./bin/llc+0x28d8d25)
Aborted (core dumped)
```

Reduced test case w/`llvm-reduce`:

```llvm
; RUN: llc -mtriple=hexagon-unknown-linux-musl -mcpu=hexagonv68 -mattr=+memops,+hvxv68,+hvx-length128b,+hvx-qfloat -O3 -o /dev/null %s

target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048"
target triple = "hexagon-unknown-linux-musl"

define <96 x i32> @f(ptr %this, ptr %0, ptr %1) {
entry:
%2 = load ptr, ptr %this, align 4
%3 = getelementptr i8, ptr %2, i32 -384
%interleaved.vec414 = load <96 x i32>, ptr %3, align 4
store <96 x i32> %interleaved.vec414, ptr %0, align 4, !noalias !0
%4 = getelementptr i8, ptr %2, i32 -768
%interleaved.vec414.1 = load <96 x i32>, ptr %4, align 4, !alias.scope !0
store <96 x i32> %interleaved.vec414.1, ptr %1, align 4, !noalias !0
%5 = getelementptr i8, ptr %2, i32 -1152
%interleaved.vec414.2 = load <96 x i32>, ptr %5, align 4, !alias.scope !0
store <96 x i32> %interleaved.vec414.2, ptr %this, align 4, !noalias !0
%interleaved.vec414.3 = load <96 x i32>, ptr %2, align 4, !alias.scope !0
ret <96 x i32> %interleaved.vec414.3
}

!0 = !{!1}
!1 = distinct !{!1, !2}
!2 = distinct !{!2, !"LVerDomain"}

```

Potential fix?

```diff
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index cfcf97067315..5391ef5ce18e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -4303,8 +4303,8 @@ HexagonTargetLowering::combineConcatOfScalarPreds(SDValue Op, unsigned BitBytes,

SDValue HexagonTargetLowering::combineConcatVectorsBeforeLegal(
SDValue Op, DAGCombinerInfo &DCI) const {
- MVT ResTy = ty(Op);
- MVT ElemTy = ResTy.getVectorElementType();
+ EVT ResTy = Op.getValueType();
+ EVT ElemTy = ResTy.getVectorElementType();

if (ElemTy != MVT::i1) {
return combineConcatOfShuffles(Op, DCI.DAG);

```