AArch64: More shuffles should be using TBL

LLVM is capable of a cute trick to avoid loading indices for tbl when byteswapping a 16xi8 vector:

```asm
rev64 v0.16b, v0.16b
ext v0.16b, v0.16b, v0.16b, #8
```

But, even if we're byteswapping multiple times in the same block, or in a loop, where loading a constant could be justified, LLVM sticks with this two instruction solution. This can be worked around by using the tbl intrinsic directly, but ideally we should be keeping things as shufflevector and letting LLVM choose the ideal sequence, I think.

This would be a great boon for RPCS3 (PS3 emulator) where 128b byteswaps are absolutely everywhere.

Here is an example:
https://godbolt.org/z/98x6s9nvG

Start with the linked Godbolt example and trace the AArch64 lowering of shufflevector, comparing it with the direct tbl intrinsic path described in the issue. Done means suitable byte-swapping shuffles can lower to TBL when that is beneficial, without requiring callers to use the intrinsic directly.

Written by the indexing model from the issue text.