[PowerPC] Poor codegen for `v2f32` operation on `f64`

See

https://godbolt.org/z/cj4Ebjrz3

```llvm
define double @insert_lane0_via_f64(double %x, float %a) {
%v = bitcast double %x to <2 x float>
%i = insertelement <2 x float> %v, float %a, i64 0
%r = bitcast <2 x float> %i to double
ret double %r
}
```

generates

```asm
.LCPI0_0:
.byte 23 # 0x17
.byte 22 # 0x16
.byte 21 # 0x15
.byte 20 # 0x14
.byte 3 # 0x3
.byte 2 # 0x2
.byte 1 # 0x1
.byte 0 # 0x0
.byte 7 # 0x7
.byte 6 # 0x6
.byte 5 # 0x5
.byte 4 # 0x4
.byte 3 # 0x3
.byte 2 # 0x2
.byte 1 # 0x1
.byte 0 # 0x0
insert_lane0_via_f64: # @insert_lane0_via_f64
.Lfunc_gep0:
addis 2, 12, .TOC.-.Lfunc_gep0@ha
addi 2, 2, .TOC.-.Lfunc_gep0@l
addis 3, 2, .LCPI0_0@toc@ha
xscvdpspn 36, 2
xxlor 34, 1, 1
addi 3, 3, .LCPI0_0@toc@l
lxvd2x 0, 0, 3
xxswapd 35, 0
vperm 2, 2, 4, 3
xxswapd 1, 34
blr
```

But the individual components generate much better assembly on their own

```llvm
define <2 x float> @bitcast_f64_to_v2f32(double %x) {
%v = bitcast double %x to <2 x float>
ret <2 x float> %v
}

define double @bitcast_v2f32_to_f64(<2 x float> %v) {
%r = bitcast <2 x float> %v to double
ret double %r
}

define <2 x float> @insert_lane0(<2 x float> %v, float %a) {
%r = insertelement <2 x float> %v, float %a, i64 0
ret <2 x float> %r
}
```

Gives

```asm
bitcast_f64_to_v2f32: # @bitcast_f64_to_v2f32
xxspltd 34, 1, 0
blr
bitcast_v2f32_to_f64: # @bitcast_v2f32_to_f64
xxswapd 1, 34
blr
insert_lane0: # @insert_lane0
xscvdpspn 1, 1
xxmrglw 0, 34, 34
xxmrghw 34, 0, 1
blr
```

So, some sort of combine is missed.

Start by reproducing the provided LLVM IR through the PowerPC backend, using the Godbolt example and comparing the combined function with the three component functions. Trace the missed combine responsible for the extra permutation and constant-load sequence, then verify that the combined operation produces code comparable to the component sequence.

Written by the indexing model from the issue text.