RISCV rvv unoptimal vector_deinterleave lowering

When a fixed-length VECTOR_DEINTERLEAVE tuple exceeded LMUL=8, the lowering recursively split its operands in registers introduces
extra instructions.

It can be optimally lowered by storing each complete operand contiguously instead. then select a legal chunk type,
and then issue segmented loads at consecutive offsets, and concatenate the corresponding result chunks.

testcase: https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll#L226

can be optimized to use segmented load to save 20+ instrucitons

Start with the testcase in llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll around line 226, then trace the fixed-length VECTOR_DEINTERLEAVE lowering and its generated instructions. Compare the current recursive split with the proposed segmented-load approach. Done means the testcase uses fewer instructions while preserving correct lowering and passes the relevant RISC-V code-generation tests.

Written by the indexing model from the issue text.