[X86][AVX512] missed fold unmasked load + masked (expand)load to unmasked load + masked (expand)mov

```c++
typedef int i32 [[clang::ext_vector_type(16)]];
typedef bool i1 [[clang::ext_vector_type(16)]];
#include
i32 src(int *a, i32 b){
i32 x = __builtin_masked_load((i1)true, a, (i32)0);
i1 mask = x > b;
i32 y = __builtin_masked_load(mask, a, (i32)0);
return y;
}

i32 tgt(int *a, i32 b){
i32 x = __builtin_masked_load((i1)true, a, (i32)0);
i32 y = x > b ? x : 0;
return y;
}

i32 src2(int *a, i32 b){
i32 x = __builtin_masked_load((i1)true, a, (i32)0);
i1 mask = x > b;
i32 y = __builtin_masked_expand_load(mask, a, (i32)0);
return y;
}

i32 tgt2(int *a, i32 b){
i32 x = __builtin_masked_load((i1)true, a, (i32)0);
i1 mask = x > b;
i32 y = _mm512_maskz_expand_epi32(__builtin_bit_cast(__mmask16, mask), x);
return y;
}
```
```asm
src(int*, int vector[16]):
vpcmpltd k1, zmm0, zmmword ptr [rdi]
vmovdqu32 zmm0 {k1} {z}, zmmword ptr [rdi]
ret

tgt(int*, int vector[16]):
vmovdqu64 zmm1, zmmword ptr [rdi]
vpcmpgtd k1, zmm1, zmm0
vmovdqa32 zmm0 {k1} {z}, zmm1
ret

src2(int*, int vector[16]):
vpcmpltd k1, zmm0, zmmword ptr [rdi]
vpexpandd zmm0 {k1} {z}, zmmword ptr [rdi]
ret

tgt2(int*, int vector[16]):
vmovdqu64 zmm1, zmmword ptr [rdi]
vpcmpgtd k1, zmm1, zmm0
vpexpandd zmm0 {k1} {z}, zmm1
ret
```
https://godbolt.org/z/nbjrrKaoe
LV sometimes generates such patterns.

Start by reproducing the src, src2, tgt, and tgt2 functions from the issue and compare their generated AVX512 assembly with the linked Godbolt example. Trace the LLVM X86 optimization path responsible for masked loads and expand loads; done means the source patterns generate the more efficient full-load plus masked move or expand sequence shown by tgt and tgt2.

Written by the indexing model from the issue text.