[hexagon] missing instructions for v81

Upstream LLVM does not recognize the `:nt` (non-temporal) hint introduced in v79 for post-increment stores and the
`dczeroa`/`dcfetch` cache-management instructions.

The downstream fork used by the Hexagon SDK toolchain does support these instructions correctly.

## Toolchain tested

- **Public (broken):** `hexagon-unknown-linux-musl-clang`, Debian clang
version 22.1.8, target `hexagon-unknown-linux-musl`, LLVM 22.
- **Reference (working):** `hexagon-llvm-mc`
(`/opt/Hexagon_SDK/6.4.0.2/tools/HEXAGON_Tools/19.0.04/Tools/bin/`),
LLVM 19.0.0.

## Affected instructions (6)

| Mnemonic | Encoding |
|---|---|
| `memb(Rx++#s4:0):nt = Rt` | `0xaa02c308` (example operands) |
| `memh(Rx++#s4:1):nt = Rt` | |
| `memw(Rx++#s4:2):nt = Rt` | `0xaa82c308` |
| `memd(Rx++#s4:3):nt = Rtt` | `0xaa8ac308` |
| `if ([!]p0) memw(Rx++#s4:2):nt = Rt` (predicated forms, all 4 sizes) | `0xaa82e308` / `0xaa82e30c` |
| `dczeroa(Rs):nt` | `0xa0c2e000` |
| `dcfetch(Rs+#0):nt` | `0x9402e000` |

## What was tested

**Assembler (public, fails):**
```
$ hexagon-unknown-linux-musl-clang -mv81 -c nt.s -o nt.o
nt.s:1:15: error: invalid operand for instruction
{ memw(r2++#4):nt = r3 }
^
```
Same result at every `-mcpu` from v79 through v81; `-mattr=help` lists no
feature flag that gates `:nt` on the post-increment/cache-op forms
(only the existing HVX-side non-temporal attributes exist).

**Disassembler (public, fails):** raw-byte disassembly of the encodings
above (e.g. `llvm-mc -disassemble -triple=hexagon -mcpu=hexagonv81`) does
not decode to the `:nt` mnemonics at any `-mcpu`.

All the6 instructions assemble and disassemble correctly at `-mcpu=hexagonv81`,
producing/matching the same encodings shown above.