[hexagon] `Q6_Vsf_vadd_VsfVsf` assigns to `qf32` instead of `sf`

Given this code

```c++
#include
#include

HVX_Vector add(const HVX_Vector& a, const HVX_Vector& b) noexcept
{
return Q6_Vsf_vadd_VsfVsf(a, b);
}
```

The compiler generates

```
add(long vector[32] const&, long vector[32] const&):
{
allocframe(r29,#0):raw
}
{
v0 = vmem(r0+#0)
}
{
v0.qf32 = vadd(v0.sf,v1.sf)
v1.cur = vmem(r1+#0)
}
{
v0.sf = v0.qf32
r31:30 = dealloc_return(r30):raw
}
```

https://godbolt.org/z/WPddbT46r

So although the `Q6_Vsf_vadd_VsfVsf` intrinsic is used, the compiler generates `v0.qf32 = vadd(v0.sf,v1.sf)` instead of `v0.sf = vadd(v0.sf,v1.sf)`. (It looks like the `Q6_Vqf32_vadd_VsfVsf` is used instead).

At least this is the documentation in hexagon_protos.h

https://github.com/llvm/llvm-project/blob/39a9ab1bb6776e16be2c74bdba66677ad991114d/clang/lib/Headers/hvx_hexagon_protos.h#L3895-L3903

For example the auto-vectorizer would produce the optimal code without `qf32` to `sf` conversion:
https://godbolt.org/z/KKEc849d3

This issue is only present if `v79` or `v81` is used. I also see the same issue when using the
`QuIC LLVM Hexagon Clang version 19.0.07`

from the Hexagon SDK with the intrinsics definition

```c++
#if __HVX_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf)
C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */

#define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv)
#endif /* __HEXAGON_ARCH___ >= 68 */
```

I also tried various compile flags according to the documentation
"LLVM C/C++ Compiler User Guide" of the Hexagon SDK but weren't able to improve it.

Why is this an issue: It produces inefficient code when chaining intrinsics:
https://godbolt.org/z/W9z7ddz4Y