SIGILL triggered in OpenBSD/Octeon by clear_cache() builtin

Since 674a17e9bbe82e8c53952fd94dcd862b17cb2d2f, a call to calculate the size of the cache lines through the `hwr_synci_step` register was added, but that access is not always meant to be enabled, and it is specifically not allowed by the OpenBSD kernel, resulting in a SIGILL when `__builtin_clear_cache()` is used.

It is important to also note that the register itself is not available for any ISA older than mips{32/64}r2, so it is likely to cause problems also in other systems than OpenBSD.

Start by tracing LLVM's __builtin_clear_cache implementation for the MIPS target, focusing on the hwr_synci_step register access. Reproduce the failure on OpenBSD/Octeon and compare behavior on ISA versions older than mips32r2/mips64r2. Done means cache clearing no longer triggers SIGILL and unsupported register access is avoided.

Written by the indexing model from the issue text.