[SLP] suboptimal asymmetric load store vectorization

found from https://github.com/gcc-mirror/gcc/commit/adc20f13b60f90c6a55d46fc6be37dfb9f4b86a0

```c
void foo (long *p, long *q, long *r)
{
long tem0 = r[0];
long tem1 = r[1];
long tem2 = r[2];
long tem3 = r[3];
tem0 = tem0 + 1;
tem1 = tem1 + 2;
tem2 = tem2 + 3;
tem3 = tem3 + 4;
p[0] = tem0;
p[1] = tem1;
q[0] = tem0;
q[1] = tem1;
q[2] = tem2;
q[3] = tem3;
}

void bar (long *p, long *q, long *r)
{
long tem0 = r[0];
long tem1 = r[1];
long tem2 = r[2];
long tem3 = r[3];
tem0 = tem0 + 1;
tem1 = tem1 + 2;
tem2 = tem2 + 3;
tem3 = tem3 + 4;
p[0] = tem0;
p[1] = tem1;
p[2] = tem2;
p[3] = tem3;
q[0] = tem0;
q[1] = tem1;
q[2] = tem2;
q[3] = tem3;
}
```
gcc:
```asm
foo:
vmovdqa .LC0(%rip), %ymm0
vpaddq (%rdx), %ymm0, %ymm0
vmovdqu %xmm0, (%rdi)
vmovdqu %ymm0, (%rsi)
vzeroupper
ret
bar:
vmovdqa .LC0(%rip), %ymm0
vpaddq (%rdx), %ymm0, %ymm0
vmovdqu %ymm0, (%rdi)
vmovdqu %ymm0, (%rsi)
vzeroupper
ret
.LC0:
.quad 1
.quad 2
.quad 3
.quad 4
```
clang:
```asm
.LCPI0_0:
.quad 1
.quad 2
.LCPI0_1:
.quad 3
.quad 4
foo:
vmovdqu (%rdx), %xmm0
vmovdqu 16(%rdx), %xmm1
vpaddq .LCPI0_0(%rip), %xmm0, %xmm0
vpaddq .LCPI0_1(%rip), %xmm1, %xmm1
vmovdqu %xmm0, (%rdi)
vmovdqu %xmm0, (%rsi)
vmovdqu %xmm1, 16(%rsi)
retq

.LCPI1_0:
.quad 1
.quad 2
.quad 3
.quad 4
bar:
vmovdqu (%rdx), %ymm0
vpaddq .LCPI1_0(%rip), %ymm0, %ymm0
vmovdqu %ymm0, (%rdi)
vmovdqu %ymm0, (%rsi)
vzeroupper
retq
```
https://godbolt.org/z/dMc357ajo

Start with the foo and bar C reproducers in the issue and compile them using the linked Godbolt example. Compare the generated assembly, focusing on the asymmetric stores in foo and the differing vectorization behavior. Done means the suboptimal foo case is addressed while both examples remain correct.

Written by the indexing model from the issue text.