[PowerPC] PPC32 pwr8: v1i128 arguments beyond V2-V13 and variadic v1i128 have no calling-convention assignment

On 32-bit PowerPC with P8 vector support (`-mtriple=powerpc-unknown-linux-gnu
-mcpu=pwr8`), `CC_PPC32_SVR4` assigns `v1i128` arguments to AltiVec registers
V2-V13, but the common vector stack-fallback list omits `v1i128` — `f128` has
its own 16-byte stack rule, `v1i128` has none — and `CC_PPC32_SVR4_VarArg`
delegates to that common table only. Two consequences, both reproducible on
current main and on release `llc` 22.1.8, and both independent of #214522
(which only adds the missing formal-lowering register-class cases; the
failures below reproduce identically with and without that patch):

**Fixed arguments beyond the registers fail.** Thirteen fixed `v1i128`
arguments exhaust V2-V13 and, with no stack fallback to spill to, abort:

```
LLVM ERROR: unable to allocate function argument #12
```

```llvm
target triple = "powerpc-unknown-linux-gnu"

define void @thirteen(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c,
<1 x i128> %d, <1 x i128> %e, <1 x i128> %f,
<1 x i128> %g, <1 x i128> %h, <1 x i128> %i,
<1 x i128> %j, <1 x i128> %k, <1 x i128> %l,
<1 x i128> %m, ptr %p) {
entry:
store <1 x i128> %m, ptr %p, align 16
ret void
}
```

**Variadic v1i128 miscompiles silently in release builds.** A variadic
`<1 x i128>` argument has no assignment at all. An assertions build aborts in
call lowering ("Call operand #1 has unhandled type v1i128"); release `llc`
22.1.8 exits 0 and generates code that never materialises the operand — the
call is emitted with the `i32` argument only:

```llvm
target triple = "powerpc-unknown-linux-gnu"

declare void @sink(i32, ...)

define void @caller(<1 x i128> %x) {
entry:
call void (i32, ...) @sink(i32 0, <1 x i128> %x)
ret void
}
```

Release `llc` 22.1.8 output for `@caller` (`-mcpu=pwr8`): the `i32` is set
up, `%x` is absent:

```asm
caller:
mflr 0
stwu 1, -16(1)
stw 0, 20(1)
li 3, 0
crxor 6, 6, 6
bl sink
...
```

A stack fallback for `v1i128` in the common table, next to the existing
`f128` rule, looks like the natural direction, but I don't want to guess at
the 32-bit SVR4 vector ABI: whether the `f128` condition transfers to P8
`v1i128`, and what the big/little-endian stack layout should be, needs a
call from someone who knows this ABI. Caller and callee tests should land
with whatever rule is chosen.

Found while verifying #214522, which fixes the adjacent formal-lowering
crash for register-resident `f128`/`v1i128` arguments and neither causes
nor fixes the two gaps above.

## Tool use

Per the [LLVM AI Tool Use Policy](https://llvm.org/docs/AIToolPolicy.html): AI
tools were involved throughout the preparation of this report. I am
accountable for its contents.

Assisted-by: OpenAI Codex
Assisted-by: Claude Code
Assisted-by: Kimi
Assisted-by: DeepSeek

Start with the named CC_PPC32_SVR4 and CC_PPC32_SVR4_VarArg tables, comparing the existing f128 stack-fallback rule with the common vector fallback list. Reproduce both cases with llc for the stated PowerPC triple and pwr8 CPU, then add caller and callee tests whose expected results reflect the ABI rule selected for fixed and variadic v1i128 arguments.

Written by the indexing model from the issue text.