[X86] using f64/f32/f16 division to lower scalar i8/16/32 division

separated from #201319.

Currently, vector integer division have been lowered to vector FP division by #205263

But for i8/i16/i32 scalar integer division, lowering to FP division is also profitable:

https://lemire.me/blog/2017/11/16/fast-exact-integer-divisions-using-floating-point-operations

Even for uarch like tigerlake that has a dedicated integer division unit, FP division is still faster:

```
populate_int32(inum64,iarray32,N) : 3.308 cycles per operation (best) 3.943 cycles per operation (avg)
populate_int32viafloat64(inum64,iarray32,N) : 2.230 cycles per operation (best) 2.250 cycles per operation (avg)
```

So, FP division provides faster, pipelined, untrapable scalar integer division, and the register allocation is also more flexible.

Scalar cases are different from vector cases:

1. unlike #214431, vdivsh is not slow, so the use of f16 division may not require guard by tuning.
https://uops.info/html-instr/VDIVSH_XMM_XMM_XMM.html

2. vdivs* also supported SAE, so strictfp should also be supported on avx512.

3. GPR div instructions also return remainders, so when doing this, whether the remainder is used should be considered.