[AArch64] missed fold vector fptoui(fdiv(uitofp(x),uitofp(y))) or fptosi(fdiv(sitofp(x),sitofp(y))) into udiv(x,y) or sdiv(x,y) for sve

This is backend version of #205502. The difference is folding in aarch64 backend doesn't need to account for special cases such as division by zero or INT_MIN/-1:

https://support.arm.com/documentation/ddi0487/mc/-Part-C-The-AArch64-Instruction-Set/-Chapter-C3-A64-Instruction-Set-Overview/-C3-7-Data-processing---register/-C3-7-10-Multiply-and-divide

>If a signed integer division (INT_MIN / -1) is performed where INT_MIN is the most negative integer value representable in the selected register size, then the result overflows the signed integer range. No indication of this overflow is produced and the result that is written to the destination register is INT_MIN.

>A division by zero results in a zero being written to the destination register, without any indication that the division by zero occurred.

https://llvm.org/docs/LangRef.html#fptoui-to-instruction

>The ‘fptoui’ instruction converts its [floating-point](https://llvm.org/docs/LangRef.html#t-floating) operand into the nearest (rounding towards zero) unsigned integer value. If the value cannot fit in ty2, the result is a [poison value](https://llvm.org/docs/LangRef.html#poisonvalues).

>The ‘fptosi’ instruction converts its [floating-point](https://llvm.org/docs/LangRef.html#t-floating) operand into the nearest (rounding towards zero) signed integer value. If the value cannot fit in ty2, the result is a [poison value](https://llvm.org/docs/LangRef.html#poisonvalues).

Start by comparing the AArch64 backend's SVE handling with the related issue #205502, then trace where fptoui/fptosi, fdiv, and integer division patterns are considered. Use the Arm instruction-set behavior and LLVM LangRef excerpts in the issue as constraints; done means the specified conversions fold to udiv or sdiv for SVE without violating those semantics.

Written by the indexing model from the issue text.