Register coalescer joining large number of subreg copies with imm src causing machine scheduler to bail out

In true16 mode we are seeing the following transformation from coalescer

```asm
%1 = v_mov_b16_t16_e64 ...
%2.hi16 = copy %1
%2.lo16 = VALU16
...
%3.hi16 = copy %1
%3.lo16 = VALU16
....
%4.hi16 = copy %1
%4.lo16 = VALU16
```

to

```asm
%1 = v_mov_b16_t16_e64 ...
%2.hi16 = copy %1
%2.lo16 = VALU16
...
%2.lo16 = VALU16 (reuse %2 and repeat)
....
%2.lo16 = VALU16 (reuse %2 and repeat)
```

When the number of subreg copy increase this transformation inserts a large number of WAR hazards on the reused virutal reg %2. The machine scheduler bail out getting higher reg pressure after sorting. This ends up being higher compile time, and more spilling in heavy reg pressure use case.

Upon discussion, a possible solution might be doing an early remateraliztion before register coalescer pass, and replace these subreg copy with `mov`.

Start by reproducing the true16 transformation described in the issue, then inspect the register coalescer and machine scheduler behavior around subregister copies and reused virtual registers. Compare the resulting WAR hazards, register pressure, compile time, and spilling; done means the problematic transformation no longer causes the scheduler bailout and associated regressions.

Written by the indexing model from the issue text.