[NVPTX][SDAG] Slow compile times when lowering wide vector reduction operations

IR:

```llvm
; ./bin/llc test.ll
target datalayout = "e-p:64:64-i64:64-i128:128-v16:16-v32:32-n16:32:64-S32"
target triple = "nvptx64-nvidia-cuda"

declare float @llvm.vector.reduce.fadd.v65536f32(float, <65536 x float>)

define void @kernel(ptr addrspace(1) %out, ptr addrspace(1) %in) {
entry:
%val = load <65536 x float>, ptr addrspace(1) %in, align 32
%mul = fmul <65536 x float> %val, %val
%res = call float @llvm.vector.reduce.fadd.v65536f32(float 0.000000e+00, <65536 x float> %mul)
store float %res, ptr addrspace(1) %out, align 4
ret void
}
```

We don't seem to handle vector reduction operations of wide (illegal) types properly, as the above code is lowered by trying to emit an enormous DAG, leading to pathological compile times (~2mins, although it drops to seconds when the compiler is allowed to lower the reduction into a tree via `reassoc` flag).

It may be worth revisiting the compilation strategy, perhaps expanding the reduction into a loop for widths above threshold, rather than a linear chain:

https://github.com/llvm/llvm-project/blob/62bbe3fffc16d77a07cfbbb9333ef19fd01b135b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h#L93-L98

Reproduce the case with the supplied IR using ./bin/llc test.ll, then inspect llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h around the linked lines and the reduction-lowering path. Compare the normal and reassociated reductions; done means wide illegal vector reductions no longer build a pathological linear DAG or take minutes to compile.

Written by the indexing model from the issue text.