amdgpu tblgen of register-banks and register-info being slow

I've looked at why generation of register-banks and register-info is so slow for amdgpu.

tblgen parses the .td file, resolving references in records. It does so unconditionally while parsing. To generate the reg-banks and reg-info it parses AMDGPU.td which contains all .td files. But it only needs a subset of the information.

To prove how much it helps to only parse the needed stuff I tried:

```
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index a1298e5969ea..50877402c523 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2929,7 +2929,3 @@ include "GCNProcessors.td"
include "AMDGPUInstrInfo.td"
include "SIRegisterInfo.td"
include "AMDGPURegisterBanks.td"
-include "AMDGPUInstructions.td"
-include "SIInstrInfo.td"
-include "AMDGPUCallingConv.td"
-include "AMDGPUSearchableTables.td"
```

With https://github.com/llvm/llvm-project/pull/208297 applied the times go from roughly 15 secs to 10 secs. Perhaps the .td files can be reorganized to speedup the tblgen phase?

Start with llvm/lib/Target/AMDGPU/AMDGPU.td and its includes for register-banks and register-info, then review the timing comparison and changes in pull request 208297. Run the relevant AMDGPU tblgen generation before and after any .td reorganization, verifying that generated outputs remain correct while the roughly 15-second phase is reduced.

Written by the indexing model from the issue text.