[RISCV] Remove performReverseEVLCombine and performVP_STORECombine

These combines convert a reverse + load/store into a strided load/store with stride -1. However a `vlse.v` or `vsse.v` isn't always profitable, and depends on the target and types. We should remove these combines and instead do this as a cost driven transform in the loop vectorizer, see https://github.com/llvm/llvm-project/issues/204154

Below are the reciprocal throughput measurements on a bpi-f3 for each approach:

| EEW | LMUL | VL | A: vle+vrgather | B: vlse(-stride) | Speedup B/A | Highest throughput |
|----:|-----:|----:|----------------:|-----------------:|:-----------:|:-------|
| 8 | 1 | 32 | 5.0 | 32.0 | 0.16x | A |
| 8 | 2 | 64 | 16.0 | 64.0 | 0.25x | A |
| 8 | 4 | 128 | 64.0 | 128.0 | 0.50x | A |
| 8 | 8 | 256 | 263.0 | 256.0 | 1.03x | tie |
| 16 | 1 | 16 | 5.0 | 16.0 | 0.31x | A |
| 16 | 2 | 32 | 16.0 | 32.0 | 0.50x | A |
| 16 | 4 | 64 | 64.0 | 64.0 | 1.00x | tie |
| 16 | 8 | 128 | 263.0 | 128.0 | 2.05x | B |
| 32 | 1 | 8 | 5.0 | 8.0 | 0.63x | A |
| 32 | 2 | 16 | 16.0 | 16.0 | 1.00x | tie |
| 32 | 4 | 32 | 64.0 | 32.0 | 2.00x | B |
| 32 | 8 | 64 | 263.0 | 64.0 | 4.11x | B |
| 64 | 1 | 4 | 5.0 | 4.0 | 1.25x | B |
| 64 | 2 | 8 | 16.0 | 8.0 | 2.00x | B |
| 64 | 4 | 16 | 64.0 | 16.0 | 4.00x | B |
| 64 | 8 | 32 | 263.0 | 32.0 | 8.22x | B |

| EEW | LMUL | VL | A: vrgather+vse | B: vsse(-stride) | Speedup B/A | Highest throughput |
|----:|-----:|----:|----------------:|-----------------:|:-----------:|:-------|
| 8 | 1 | 32 | 5.0 | 32.0 | 0.16x | A |
| 8 | 2 | 64 | 16.0 | 64.0 | 0.25x | A |
| 8 | 4 | 128 | 64.0 | 128.0 | 0.50x | A |
| 8 | 8 | 256 | 256.0 | 256.0 | 1.00x | tie |
| 16 | 1 | 16 | 5.0 | 16.0 | 0.31x | A |
| 16 | 2 | 32 | 16.0 | 32.0 | 0.50x | A |
| 16 | 4 | 64 | 64.0 | 65.0 | 0.98x | tie |
| 16 | 8 | 128 | 256.0 | 130.3 | 1.97x | B |
| 32 | 1 | 8 | 5.0 | 8.0 | 0.63x | A |
| 32 | 2 | 16 | 16.0 | 16.0 | 1.00x | tie |
| 32 | 4 | 32 | 64.0 | 32.0 | 2.00x | B |
| 32 | 8 | 64 | 256.0 | 64.0 | 4.00x | B |
| 64 | 1 | 4 | 5.0 | 5.9 | 0.85x | A |
| 64 | 2 | 8 | 16.0 | 12.0 | 1.33x | B |
| 64 | 4 | 16 | 64.0 | 16.0 | 4.00x | B |
| 64 | 8 | 32 | 256.0 | 32.0 | 8.00x | B |

Locate the RISC-V implementations of performReverseEVLCombine and performVP_STORECombine and inspect how they turn reverse load/store patterns into negative-stride operations. Read issue 204154 and the loop vectorizer entry points it identifies before changing behavior. Done means the combines are removed and the decision is handled by the intended cost-driven vectorizer transform, with relevant compiler tests updated or checked.

Written by the indexing model from the issue text.