[AMDGPU] Add Post-RA peephole to optimize True16 16-bit mov and 16-bit zero

On the true16 code generation path, we often see cases where one v_mov_b16 moves 16 bits from some register to the hi or low half (equivalent to a 16 bit shift) and another v_mov_b16 writes 0 to the other half of that register. We can do this in one instruction lshlrev or lshrrev. Those shift instructions can can do 16-bit data movement and write 0 in the other 16 bits in one instruction. See an example here:
https://github.com/llvm/llvm-project/pull/190036#discussion_r3024404860

https://github.com/llvm/llvm-project/issues/190796 fixed one case that was possible to be fixed in ISel. In other cases, we cannot determine the optimal instruction sequence until after register allocation has happened and we know whether the incoming 16-bit value has been placed in the lo or hi 16 bits. We can add an optimization to si-pre-emit-peephole to change to the optimal sequence.

There is a similar case discussed here:
https://github.com/llvm/llvm-project/pull/206058
The true16 pattern can be changed to the one discussed in the comment, and then the post-RA peephole can optimize it.