Tablegen of ARM prefers shifted regs over constants

So, LLVM's arm backend and tablgen have a problem:

consider the following:

; V81M-BE-NEXT: movs r1, #0
; V81M-BE-NEXT: sub.w r0, r1, r0, lsr #24

because tablegen wants the shifted operand version. This is normally fine, but

; V81M-BE-NEXT: lsrs r0, r0, #24
; V81M-BE-NEXT: rsbs r0, r0, #0

is better overall because it takes less space and uses same instruction count. The problem is that tablegen will always choose the former. How can I configure this so that it chooses the latter when it is beneficial

Start by tracing the ARM backend's TableGen instruction-selection rules for shifted registers and constants, using the V81M-BE assembly examples as the behavioral reference. Determine how the preference is encoded and how instruction size and count are represented; done means the shorter constant-based sequence is selected when it is equally long in instructions and beneficial in code size.

Written by the indexing model from the issue text.