[AMDGPU] "Inconsistent LiveInterval" assertion in LiveIntervalUnion::extract during regalloc

Live Reproducer: https://godbolt.org/z/q1sE535EE

Compiling the following LLVM IR with `llc -mcpu=gfx1100` aborts with the assertion `SegPos.value() == &VirtReg && "Inconsistent LiveInterval"` failed during the Greedy Register Allocator.

```llvm
target triple = "amdgcn-amd-amdhsa"

define void @repro(<210 x i1> %seed, ptr %sink, i1 %enter) {
entry:
br i1 %enter, label %outer.header, label %exit

outer.header:
%outer.index = phi i32 [0, %entry], [%outer.next, %outer.latch]
%outer.vec = phi <210 x i1> [%seed, %entry], [%outer.next.vec, %outer.latch]
br label %inner.header

inner.header:
%inner.index = phi i32 [0, %outer.header], [%inner.next, %inner.latch]
%inner.vec = phi <210 x i1> [%outer.vec, %outer.header], [%inner.next.vec, %inner.latch]
%branch.bit = extractelement <210 x i1> %inner.vec, i32 0
%target.addr = select i1 %branch.bit, ptr blockaddress(@repro, %store.then), ptr blockaddress(@repro, %store.else)
indirectbr ptr %target.addr, [label %store.then, label %store.else]

store.then:
store i1 false, ptr %sink
br label %inner.latch

store.else:
store i1 false, ptr %sink
br label %inner.latch

inner.latch:
%inner.next = or i32 %inner.index, 1
%inner.next.vec = xor <210 x i1> %outer.vec, %inner.vec
%inner.done = icmp eq i32 %inner.next, 1
br i1 %inner.done, label %outer.latch, label %inner.header

outer.latch:
%outer.next = or i32 %outer.index, 1
%shuffled.vec = shufflevector <210 x i1> %outer.vec, <210 x i1> %outer.vec, <210 x i32> zeroinitializer
%outer.next.vec = xor <210 x i1> %shuffled.vec, %shuffled.vec
%outer.done = icmp eq i32 %outer.next, 1
br i1 %outer.done, label %exit, label %outer.header

exit:
ret void
}
```

llc command:

```sh
llc -mcpu=gfx1100 repro.ll
```

Error output:

```
llc: /root/llvm-project/llvm/lib/CodeGen/LiveIntervalUnion.cpp:68: void llvm::LiveIntervalUnion::extract(const llvm::LiveInterval&, const llvm::LiveRange&): Assertion `SegPos.value() == &VirtReg && "Inconsistent LiveInterval"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0. Program arguments: /opt/compiler-explorer/clang-assertions-trunk/bin/llc -o /app/output.s -x86-asm-syntax=intel -mcpu=gfx1100
1. Running pass 'CallGraph Pass Manager' on module ''.
2. Running pass 'Greedy Register Allocator' on function '@repro'
#9 0x00000000037c82d6 llvm::LiveIntervalUnion::extract(llvm::LiveInterval const&, llvm::LiveRange const&) (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x37c82d6)
#10 0x0000000003272279 llvm::LiveRegMatrix::unassign(llvm::LiveInterval const&, bool) (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x3272279)
#11 0x000000000354fd08 non-virtual thunk to llvm::RAGreedy::LRE_WillShrinkVirtReg(llvm::Register) (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x354fd08)
#12 0x00000000037d3534 llvm::LiveRangeEdit::eliminateDeadDefs(llvm::SmallVectorImpl&, llvm::ArrayRef) (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x37d3534)
#13 0x00000000037bf7f6 (anonymous namespace)::InlineSpiller::spill(llvm::LiveRangeEdit&, llvm::AllocationOrder*) InlineSpiller.cpp:0:0
...
```

Start by saving the inline LLVM IR as repro.ll and running llc -mcpu=gfx1100 to reproduce the assertion. Read llvm/lib/CodeGen/LiveIntervalUnion.cpp at LiveIntervalUnion::extract and follow the Greedy Register Allocator stack; done means the reproducer no longer aborts and a regression test covers the case.

Written by the indexing model from the issue text.