[Tracking] Byte type backend conformance

Tracking umbrella for LLVM IR `bN` backend support.

## Policy

Per [RFC: Byte type lowering in MIR](https://discourse.llvm.org/t/rfc-byte-type-lowering-in-mir/90797) and maintainer guidance: at SelectionDAG/GlobalISel entry, `bN` lowers to the same EVT/LLT as `iN` (same width). GlobalISel must match SelectionDAG.

Authoritative contract: `llvm/docs/CodeGen/ByteTypeLowering.rst` (in development; see associated patches).

## Per-target checklist

- [ ] AArch64 — SDAG + GISel `llc` tests
- [ ] AMDGPU
- [ ] ARM
- [ ] BPF
- [ ] DirectX — DXIL maps `bN` → `iN` (target-specific)
- [ ] Hexagon
- [ ] LoongArch
- [ ] MIPS
- [ ] NVPTX
- [ ] PowerPC
- [ ] RISCV
- [ ] SPIR-V
- [ ] SystemZ
- [ ] VE
- [ ] WebAssembly
- [ ] X86 — `byte-constants.ll`, `byte-ops.ll`
- [ ] Xtensa

## Shared items

- [ ] Codegen contract documentation
- [ ] GISel `ConstantByte` translation
- [ ] Multi-target conformance tests

Related: #178666 (IR byte type)