[NVPTX] assertion failure in LowerSTOREi1 on store of irregular wide vector <17 x i113>

Live Reproducer:

Compiling the following LLVM IR with `llc` triggers an assertion failure in `NVPTXTargetLowering::LowerSTOREi1`.

```llvm
target triple = "nvptx64-nvidia-cuda"

define void @repro(ptr %p) {
store <17 x i113> zeroinitializer, ptr %p
ret void
}
```

llc command:

```sh
llc reproducer.ll
```

Error output:

```
llc: /root/llvm-project/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp:3984: llvm::SDValue llvm::NVPTXTargetLowering::LowerSTOREi1(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0. Program arguments: llc -o /app/output.s
1. Running pass 'Function Pass Manager' on module ''.
2. Running pass 'NVPTX DAG->DAG Pattern Instruction Selection' on function '@repro'
#9 llvm::NVPTXTargetLowering::LowerSTOREi1(llvm::SDValue, llvm::SelectionDAG&) const
#10 llvm::NVPTXTargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const
#11 llvm::TargetLowering::LowerOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl&, llvm::SelectionDAG&) const
#12 llvm::DAGTypeLegalizer::CustomLowerNode(llvm::SDNode*, llvm::EVT, bool)
#13 llvm::DAGTypeLegalizer::ExpandIntegerOperand(llvm::SDNode*, unsigned int)
#14 llvm::DAGTypeLegalizer::run()
#15 llvm::SelectionDAG::LegalizeTypes()
#16 llvm::SelectionDAGISel::CodeGenAndEmitDAG()
#19 llvm::NVPTXDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&)
Program terminated with signal: SIGSEGV
```