[AMDGPU] llc asserts in getCopyToPartsVector on irregular-width vector return

Live Reproducer:

Compiling the following LLVM IR with `llc` triggers an assertion failure in `getCopyToPartsVector`.

```llvm
target triple = "amdgcn-amd-amdhsa"

define <4 x i63> @bf_structured_39() {
entry:
ret <4 x i63> zeroinitializer
}
```

llc command:

```sh
llc reproducer.ll
```

Error output:

```
llc: /root/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:809: void getCopyToPartsVector(llvm::SelectionDAG&, const llvm::SDLoc&, llvm::SDValue, llvm::SDValue*, unsigned int, llvm::MVT, const llvm::Value*, std::optional): Assertion `Val.getValueType() == BuiltVectorTy && "Unexpected vector value type"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0. Program arguments: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -O2
1. Running pass 'CallGraph Pass Manager' on module ''.
2. Running pass 'AMDGPU DAG->DAG Pattern Instruction Selection' on function '@bf_structured_39'
#9 getCopyToParts(...)
#10 llvm::SelectionDAGBuilder::visitRet(llvm::ReturnInst const&)
#11 llvm::SelectionDAGBuilder::visit(llvm::Instruction const&)
#14 llvm::SelectionDAGISel::runOnMachineFunction(...)
#15 llvm::AMDGPUDAGToDAGISel::runOnMachineFunction(...)
Program terminated with signal: SIGSEGV
```

Note: on a non-assertion `llc` trunk build the same input does not abort but appears to be miscompiled where each `i63` lane is truncated to 32 bits, dropping the upper 31 bits of every lane.
Non-assertion reproducer: