llvm / llvm/llvm-project

Neon BSL not being used for select

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backend:AArch64 llvm:codegen NEON
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Description

In RPCS3, for the emulation of the SPU `FCGT` instruction, I ran into this issue, where llvm would refuse to emit BSL no matter what way I would massage the IR. The only way I found to work around was with inline assembly.

Here is a godbolt that reproduces the issue:
https://godbolt.org/z/4TfqsT37K

```asm
spu_FCGTbsl:
lsr w8, w22, #3
mov w8, w8
and x8, x24, x8
ldr q0, [x25, x8]
and w8, w24, w22, lsr #10
ldr q1, [x25, w8, uxtw]
and w8, w24, w22, lsl #4
cmgt v2.4s, v0.4s, v1.4s
cmgt v3.4s, v1.4s, v0.4s
and v4.16b, v1.16b, v0.16b
fcmeq v0.4s, v0.4s, v1.4s
cmge v4.4s, v4.4s, #0
bsl v4.16b, v2.16b, v3.16b
bic v0.16b, v4.16b, v0.16b
str q0, [x25, w8, uxtw]
ret
```

```asm
spu_FCGT:
lsr w8, w22, #10
mov w8, w8
and x8, x24, x8
ldr q0, [x25, x8]
and w8, w24, w22, lsr #3
ldr q1, [x25, w8, uxtw]
and w8, w24, w22, lsl #4
fcmeq v2.4s, v1.4s, v0.4s
cmgt v3.4s, v0.4s, v1.4s
cmgt v4.4s, v1.4s, v0.4s
and v0.16b, v1.16b, v0.16b
cmlt v0.4s, v0.4s, #0
xtn v4.4h, v4.4s
mvn v2.16b, v2.16b
xtn v1.4h, v0.4s
and v0.16b, v3.16b, v0.16b
xtn v2.4h, v2.4s
bic v1.8b, v4.8b, v1.8b
xtn v0.4h, v0.4s
orr v0.8b, v0.8b, v1.8b
and v0.8b, v2.8b, v0.8b
sshll v0.4s, v0.4h, #0
str q0, [x25, w8, uxtw]
ret
```

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