llvm / llvm/llvm-project

[IPRA] IPRA Partially Clobbers FP/ST Registers, Breaking X86Stackifier Assumptions

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#196,864 0 comments 0 reactions 1 assignee Claimed by @vigbalu View on GitHub
crash-on-invalid llvm:codegen llvm:regalloc
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Description

IPRA currently updates the clobbered registers of a call instruction by limiting them to the registers explicitly used by the corresponding callee functions.

For FP and ST registers, IPRA marks only the individually used registers as clobbered instead of marking the entire register group. This behavior is inconsistent with x86 ABI conventions, where FP and ST registers are treated as all-or-nothing clobber groups.

PASS: clang -c -O1 -mllvm -enable-ipra=false test.ll
FAIL: clang -c -O1 -mllvm -enable-ipra=true test.ll

test.ll
define internal x86_fp80 @callee(x86_fp80 %a) #0 {
entry:
%mul = fmul x86_fp80 %a, %a
ret x86_fp80 %mul
}

define x86_fp80 @caller(x86_fp80 %x) {
entry:
%pre = fadd x86_fp80 %x, 0xK4000C90FDAA22168C235

%call = call x86_fp80 @callee(x86_fp80 %pre)

%post = fsub x86_fp80 %call, %x
ret x86_fp80 %post
}

attributes #0 = { noinline }

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