[X86] Regression: i128 `select` legalized to SSE chain instead of CMOV/branch

Since 964651ad515b, an `i128 select` whose arms both `mayFoldIntoVector` is replaced with a `v4i32 vselect`. DAGCombine then folds the `vselect ..., x, 0` into `and x, sext(cond)`, producing an SSE AND/shuffle chain instead of the previous CMOV/branch form.

```llvm
define i128 @test(i1 %c, i128 %a, ptr %m) {
%b = load i128, ptr %m
%sel = select i1 %c, i128 %b, i128 0
ret i128 %sel
}
```
https://godbolt.org/z/v7j8PnGx6

```asm
test: # @test
movq xmm0, qword ptr [rcx + 8] # xmm0 = mem[0],zero
movq xmm1, qword ptr [rcx] # xmm1 = mem[0],zero
punpcklqdq xmm1, xmm0 # xmm1 = xmm1[0],xmm0[0]
and edi, 1
neg edi
movd xmm0, edi
pshufd xmm0, xmm0, 0 # xmm0 = xmm0[0,0,0,0]
pand xmm0, xmm1
movq rax, xmm0
pshufd xmm0, xmm0, 238 # xmm0 = xmm0[2,3,2,3]
movq rdx, xmm0
ret
```