llvm / llvm/llvm-project

[RISC-V] `llvm.experimental.vector.compress` unnecessarily rounds up VL to next power of two

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backend:RISC-V
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LLVM
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Description

With this IR:

```llvm
define noundef <13 x i8> @compress(ptr dead_on_return noalias noundef readonly align 1 captures(none) dereferenceable(13) %arr) unnamed_addr {
start:
%vec = load <13 x i8>, ptr %arr, align 1
%mask = icmp uge <13 x i8> %vec, splat (i8 4)
%result = tail call <13 x i8> @llvm.experimental.vector.compress.v13i8(<13 x i8> %vec, <13 x i1> %mask, <13 x i8> poison)
ret <13 x i8> %result
}

```

... `llc -march=riscv64 -mattr=+v -O2` generates ([Godbolt](https://godbolt.org/z/7Pca5n4h9)):

```asm
compress:
vsetivli zero, 13, e8, m1, ta, ma
vle8.v v9, (a0)
lui a0, 2
addi a0, a0, -1
vsetivli zero, 16, e8, m1, ta, ma
vmsgtu.vi v8, v9, 3
vsetvli zero, zero, e16, m2, ta, ma
vmv.s.x v10, a0
vmand.mm v10, v8, v10
vsetvli zero, zero, e8, m1, ta, ma
vcompress.vm v8, v9, v10
ret
```

It decided to increase the VL to 16, which then required it to have to construct an additional mask of `(1 << 13) - 1` and `vmand.mm` it with the original mask. It could've just been:

```asm
compress:
vsetivli zero, 13, e8, m1, ta, ma
vle8.v v9, (a0)
vmsgtu.vi v0, v9, 3
vcompress.vm v8, v9, v0
ret
```

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