[X86] Missed Fold: `vgf2p8affineqb(x, M1, imm8) & C` => `vgf2p8affineqb(x, M2, imm8 & C)`

Given that the matrix in `vgf2p8affineqb` selects which bits of the input are XORed together for each output position, a zero row/byte set the output bit to zero. This can be used to fold ANDs by splatted 8-bit constants that occur after, by zeroing a row if a given bit of the constant is not set, in reverse order (to match the matrix's behavior).

Additionally, the immediate also needs to be directly ANDed with the constant as it applies a XOR after the main transformation. Only seem beneficial when the matrix is a constant.

```asm
bitRevMaskUpper_src:
gf2p8affineqb xmm0, xmmword ptr [rip + .LCPI0_0], 0
pand xmm0, xmmword ptr [rip + .LCPI0_1]
ret
```

```asm
bitRevMaskUpper_tgt:
gf2p8affineqb xmm0, xmmword ptr [rip + .LCPI1_0], 0
ret
```

https://godbolt.org/z/3qxac4eTh

Run the linked Godbolt example first to reproduce the missed fold involving vgf2p8affineqb and the following pand. Then trace the compiler's x86 handling of this instruction and verify that the constant matrix and immediate are folded as described. Done means the example produces the target instruction sequence without the redundant AND.

Written by the indexing model from the issue text.