[RISCV] ICE with -verify-machineinstrs after Register Coalescer

llc crashes on the following example after register coalescer: https://godbolt.org/z/T546f4rv5
```
# Machine code for function foo: NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $x10 in %3, $x11 in %4

0B bb.0.entry:
successors: %bb.1(0x80000000); %bb.1(100.00%)
liveins: $x10, $x11
16B %4:gpr = COPY $x11
32B %3:gpr = COPY $x10
48B undef %39.sub_vrm1_0:vrm8 = PseudoVMV_S_X undef %39.sub_vrm1_0:vrm8(tied-def 0), %3:gpr, 16, 6
96B undef %39.sub_vrm1_0:vrm8 = PseudoVMV_S_X %39.sub_vrm1_0:vrm8(tied-def 0), $x0, 16, 6
144B undef %37.sub_vrm1_0:vrm2 = PseudoVMV_V_I_M1 undef %37.sub_vrm1_0:vrm2(tied-def 0), 1, 16, 6, 0
176B %37.sub_vrm1_1:vrm2 = INIT_UNDEF
224B %27:vrm2 = COPY %39.sub_vrm2_0:vrm8
240B early-clobber %27:vrm2 = PseudoVSLIDEUP_VI_M2 %27:vrm2(tied-def 0), %37:vrm2, 2, 3, 6, 0
256B %39.sub_vrm4_1:vrm8 = INIT_UNDEF
304B %39.sub_vrm2_1:vrm8 = INIT_UNDEF
352B %39.sub_vrm1_1:vrm8 = INIT_UNDEF
400B early-clobber %22:vr = PseudoVMSLE_VI_M8 %39:vrm8, -1, 16, 6
432B %1:gpr = PseudoVMV_X_S %22:vr, 4
448B undef %46.sub_vrm1_0:vrm2 = PseudoVMV_S_X undef %46.sub_vrm1_0:vrm2(tied-def 0), $x0, 16, 6
480B %46.sub_vrm1_1:vrm2 = INIT_UNDEF
544B early-clobber %27:vrm2 = PseudoVSLIDEUP_VI_M2 %27:vrm2(tied-def 0), %46:vrm2, 3, 4, 6, 0
576B undef %39.sub_vrm2_0:vrm8 = COPY %27:vrm2
592B %39.sub_vrm4_1:vrm8 = INIT_UNDEF
640B %39.sub_vrm2_1:vrm8 = INIT_UNDEF
688B early-clobber %30:vr = PseudoVMSLE_VI_M8 %39:vrm8, -1, 16, 6
720B %2:gpr = PseudoVMV_X_S %30:vr, 4
736B %32:gpr = SLLI %2:gpr, 48

752B bb.1.for.body.us:
; predecessors: %bb.0, %bb.1
successors: %bb.1(0x7c000000), %bb.2(0x04000000); %bb.1(96.88%), %bb.2(3.12%)

768B BNE %32:gpr, $x0, %bb.1
784B PseudoBR %bb.2

800B bb.2.for.cond13.preheader.us:
; predecessors: %bb.1
successors: %bb.4(0x40000000), %bb.3(0x40000000); %bb.4(50.00%), %bb.3(50.00%)

816B %33:gpr = ANDI %4:gpr, 1
832B BNE %33:gpr, $x0, %bb.4
848B PseudoBR %bb.3

864B bb.3.for.body23.us.us499.us.us.us.preheader:
; predecessors: %bb.2
successors: %bb.8(0x50000000), %bb.7(0x30000000); %bb.8(62.50%), %bb.7(37.50%)

880B BNE %1:gpr, $x0, %bb.8
896B PseudoBR %bb.7

912B bb.4.for.body23.us.us484.us.us.us.preheader:
; predecessors: %bb.2
successors: %bb.6(0x50000000), %bb.5(0x30000000); %bb.6(62.50%), %bb.5(37.50%)

928B BNE %2:gpr, $x0, %bb.6
944B PseudoBR %bb.5

960B bb.5.vector.ph3672:
; predecessors: %bb.4

976B PseudoRET

992B bb.6.for.body30.us351.us.us.us611.us.us:
; predecessors: %bb.4

1008B PseudoRET

1024B bb.7.vector.ph4767:
; predecessors: %bb.3

1040B PseudoRET

1056B bb.8.for.body30.us363.us449.us.us.us.us:
; predecessors: %bb.3

1072B PseudoRET

# End machine code for function foo.

*** Bad machine code: Multiple connected components in live interval ***
- function: foo
- interval: %39 [48r,96r:2)[96r,256r:0)[256r,304r:1)[304r,352r:3)[352r,400r:4)[576r,592r:5)[592r,640r:6)[640r,688r:7) 0@96r 1@256r 2@48r 3@304r 4@352r 5@576r 6@592r 7@640r L0000000000000004 [352r,400r:1)[576r,688r:3) 0@x 1@352r 2@x 3@576r L0000000000000018 [304r,400r:1)[640r,688r:5) 0@x 1@304r 2@x 3@x 4@x 5@640r L0000000000000002 [48r,96r:1)[96r,400r:0)[576r,688r:2) 0@96r 1@48r 2@576r L00000000000001E0 [256r,400r:1)[592r,688r:4) 0@x 1@256r 2@x 3@x 4@592r weight:0.000000e+00
0: valnos 0 1 2 3 4
1: valnos 5 6 7
```

Reproduce the llc crash from the linked Godbolt example with -verify-machineinstrs after the register coalescer. Start by tracing the register coalescer and machine-instruction verification around the reported “Multiple connected components in live interval” for %39. Done means the example no longer crashes and machine-instruction verification accepts the resulting code.

Written by the indexing model from the issue text.