Missed Redundant Load Elimination After Same-Value Store

The following reduced IR is derived from https://github.com/llvm/llvm-project/blob/3b76b85b15a3e7aa004814944f6237f131b95961/llvm/include/llvm/ADT/SmallPtrSet.h#L170

https://godbolt.org/z/z1qGTco7o
alive2: https://alive2.llvm.org/ce/z/6ySFsT

In the reduced IR, `%1` is stored with `0`, and the only intervening store (`store i32 0, ptr %0`) writes the same value. Even if `%0` and `%1` alias, the value at `%1` remains 0, so the load always returns 0 and is redundant.

```llvm
define i32 @_ZN4llvm19SmallPtrSetImplBase10insert_impEPKv(ptr %0, ptr %1) {
store i32 0, ptr %1, align 4
store i32 0, ptr %0, align 4
%3 = load i32, ptr %1, align 4
ret i32 %3
}
```

Expected:
```llvm
define i32 @tgt(ptr %0, ptr %1) {
store i32 0, ptr %1, align 4
store i32 0, ptr %0, align 4
ret i32 0
}
```