[X86] Remove TuningSlowSHLD / isSHLDSlow and move LowerFunnelShift i32/i64 SHLD/SHRD expansion into MachineCombiner

isSHLDSlow targets always expand funnel shifts in SelectionDAG, sometimes unintentionally affecting register pressure.

Make i32/i64 FSHL/FSHR always legal and optionally expand to OR(SHL(),LSHR()) patterns using a X86InstrInfo::genAlternativeCodeSequence X86MachineCombinerPattern entry (if not building for MinSize/OptSize).

This will require the scheduler model numbers for SHLD/SHRD to be confirmed (some AMD targets in particular have been lazy and tagged many instructions as WriteMicrocoded).

This will probably require us to improve MachineCombiner register pressure handling as well.