[RISC-V] quad widening multiply-accumulate is not vectorized, when the destination element width is not supported in the vector extension

This function:

``` C
void
mac (int64_t* dst, int16_t *a, int16_t *b, uint16_t len)
{
for (uint16_t i=0; i < len; i++)
dst[i] += (int64_t) a[i] * (int64_t) b[i];
}
```

Is vectorized when compiled for Zve64x. When compiling for Zve32x, it is not vectorized. The 64-bit widening multiplication has to be emulated through mul and mulh. This happens for the scalar version.
Diagnostics report that

> remark: the cost-model indicates that interleaving is not beneficial [-Rpass-missed=loop-vectorize]

My expectation would be that the vectorization is still beneficial, especially since Zve32x has the same capabilities as the scalar ISA for emulating this behavior.

https://godbolt.org/z/4Yo4cqojd

Start with the C reproducer and compile it for Zve32x and Zve64x using the linked Compiler Explorer example. Read the RISC-V vectorizer cost-model path responsible for the missed interleaving decision and compare its treatment of emulated widening multiplication. Done means the Zve32x loop is vectorized when the cost model shows it is beneficial, with regression coverage added in the relevant LLVM tests.

Written by the indexing model from the issue text.