[AMDGPU][CodeGen] Reg. Coalescer doesn't update live info when replacing COPY by IMPLICIT_DEF with subreg operand without live info

In some situations, Register Coalescer's input may contain a sub-register without live subranges, even though the virtual register does. In such cases, if the subreg is used in a COPY, it will be considered undef and the Register Coalescer will try to coalesce it to the next instruction. If it can't, it will transform it into an IMPLICIT_DEF, removing the subreg use.
The problem arises when that subreg COPY corresponds to the end of a live interval segment of the virtual register, because replacing it by IMPLICIT_DEF, removes the use, leaving the register interval incorrect as shown in this example:
```
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=register-coalescer -o - %s | FileCheck %s
--- |
define void @test() {
ret void
}
---
name: test
tracksRegLiveness: true
body: |
bb.0:

%0:vgpr_32 = IMPLICIT_DEF
undef %9.sub0:sgpr_64 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
%12:sgpr_32 = COPY %9.sub1:sgpr_64, implicit $exec
%16:vgpr_32 = V_MOV_B32_e32 %12:sgpr_32, implicit $exec

S_ENDPGM 0
...
```
Here, `%9` live intervals before register coalescer are `%9 [32r,48r:0) 0@32r L0000000000000003 [32r,32d:0) 0@32r weight:0.000000e+00`.

The resulting codegen is:
```
0B bb.0:
16B %0:vgpr_32 = IMPLICIT_DEF
32B dead undef %9.sub0:sgpr_64 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
48B %12:sgpr_32 = IMPLICIT_DEF
64B dead %16:vgpr_32 = V_MOV_B32_e32 %12:sgpr_32, implicit $exec
80B S_ENDPGM 0
```
With no changes in live intervals, so register %9 is live at an incorrect index (48B).
I believe the live information for register %9, after coalescing, should be
`%9 [32r,32d:0) 0@32r L0000000000000003 [32r,32d:0) 0@32r weight:0.000000e+00`

A proposal fix for this issue is in: https://github.com/llvm/llvm-project/pull/175986