LLVM generates storing and loading from msr NZCV when ANDS has multiple uses

```IR
%c0 = icmp sgt i32 %s0, %s1
%c1 = icmp ne i32 %s2, %s3
%a = and i1 %c0, %c1
%s = select i1 %a, i32 %y, i32 %x
%o = call i32 @callee(i32 %s)
%z1 = select i1 %a, i32 %o, i32 %y
%p = call i32 @callee(i32 %z1)
ret i32 %p
```

Generates:
```armasm
; CHECK-SD-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; CHECK-SD-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; CHECK-SD-NEXT: mov x19, x5
; CHECK-SD-NEXT: cmp w0, w1
; CHECK-SD-NEXT: ccmp w2, w3, #4, gt
; CHECK-SD-NEXT: mrs x20, NZCV
; CHECK-SD-NEXT: csel w0, w5, w4, ne
; CHECK-SD-NEXT: bl _callee
; CHECK-SD-NEXT: msr NZCV, x20
; CHECK-SD-NEXT: csel w0, w0, w19, ne
; CHECK-SD-NEXT: bl _callee
; CHECK-SD-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-SD-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; CHECK-SD-NEXT: ret
```
Loading and storing to NZCV is not ideal as these are system registers.
Especially when we can just replace them with alternatives.