RegisterCoalescer: Ignore zero extended during coalescing

Given the following IR:

```llvm
define i64 @fn1(i64 %arg, ptr %arg1) {
%i = trunc i64 %arg to i32
%i4 = load i8, ptr %arg1
%i5 = zext i8 %i4 to i32
%i6 = and i32 %i, -256
%i7 = or i32 %i6, %i5
%i12 = zext i32 %i7 to i64
ret i64 %i12
}
```

The assembly instructions should be

```asm
movl %edi, %eax
movb (%rsi), %al
retq
```

But the llc emits `movq %rdi, %rax` for the first instruction: https://llvm.godbolt.org/z/ene7ETKno.