[CIR] Upstream handling of X86 builtins

### Overview
This is an umbrella task for all X86 builtin upstreaming. There are enough X86-specific builtins that creating separate issues for each logical group is not practical. Many people can work on this in parallel, if we can successfully coordinate the work to avoid overlap as much as possible. To that end, I am adding a partial list here of the builtins that need to be upstreamed. If you would like to contribute to this task, please comment saying which builtin(s) you are working on.

I will remove builtins from this list as they are upstreamed.

Please check the table below before beginning work to make sure no one else is working on the builtins you are targeting. If you have any questions, please comment here tagging @andykaylor.

### Needed builtins

| Builtin group | Assignee |
| --- | --- |
| rdtsc, rdtscp | @adit4443ya |
| lzcnt, tzcnt | @Luhaocong |
| undef | @Thibault-Monnier |
| vec_ext | @Thibault-Monnier |
| vec_set | @jacquesguan |
| xsave, xrstor | @medhatiwari |
| masked store | @woruyu |
| masked load | @woruyu |
| convert to mask | @MarwanTarik |
| compress store | @AnkitDubeycs25 |
| gather | @badumbatish |
| scatter | @badumbatish |
| vinsert, shuffle, blend , perm | @Thibault-Monnier |

Many more builtins are needed but not yet implemented in the incubator. I will create a separate issue for that. work.

### Existing incubator tests
clang/test/CIR/CodeGen/X86/*