[AArch64] Use zero register directly for inline assembly

Forwarded on from a downstream report: https://github.com/ClangBuiltLinux/linux/issues/2127

GCC directly generates `xzr` or `wzr` for the `rZ` constraint when the `%x` or `%w` modifier are used, whereas clang always stores to an intermediate register.

```
void write_zero_x(volatile unsigned long *addr)
{
asm volatile("str %x1, %0\n" : : "Qo" (*addr), "rZ" (0));
}

void write_zero_w(volatile unsigned long *addr)
{
asm volatile("str %w1, %0\n" : : "Qo" (*addr), "rZ" (0));
}
```

GCC 15.2.0:

```
$ aarch64-linux-gcc -O2 -c test.c

$ llvm-objdump -dr test.o

test.o: file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 :
0: f900001f str xzr, [x0]
4: d65f03c0 ret

0000000000000008 :
8: b900001f str wzr, [x0]
c: d65f03c0 ret
```

clang @ cd33c6b68e7010679517416e87a8abd860bdc747:

```
$ clang --target=aarch64-linux -O2 -c test.c

$ llvm-objdump -dr test.o

test.o: file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 :
0: 2a1f03e8 mov w8, wzr
4: f9000008 str x8, [x0]
8: d65f03c0 ret

000000000000000c :
c: 2a1f03e8 mov w8, wzr
10: b9000008 str w8, [x0]
14: d65f03c0 ret
```

Reproduce the two AArch64 examples with clang and inspect the inline-assembly constraint handling and AArch64 code-generation entry points. Done means clang emits xzr or wzr directly for the rZ constraint with the %x or %w modifier, with a regression test covering both functions.

Written by the indexing model from the issue text.