AMDGPU register classes including pseudo-registers should not be allocatable

Several of the SGPR register classes, particularly [SReg_32_XM0_XEXEC](https://github.com/llvm/llvm-project/blob/487cdf14f67e95f61a42389bd168b32c00995ea4/llvm/lib/Target/AMDGPU/SIRegisterInfo.td#L786) include non-allocatable source values.

These classes should be split up. The cases that include the non-allocatable source values should only be used in an isAllocatable=0 class used as the register class of source operands, and not the same register class as used for virtual registers

Start with the SReg_32_XM0_XEXEC definition in llvm/lib/Target/AMDGPU/SIRegisterInfo.td, then inspect the other SGPR register classes that include non-allocatable source values. Trace how these classes are used for source operands and virtual registers; done means the non-allocatable cases are separated into isAllocatable=0 classes without being used for virtual registers.

Written by the indexing model from the issue text.